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STW5093
2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
FEATURES: Complete CODEC and FILTER system including: 14 BIT LINEAR ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS. 8 BIT COMPANDED ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS ALAW OR -LAW. TRANSMIT AND RECEIVE BAND-PASS FILTERS ACTIVE ANTIALIAS NOISE FILTER. Phone Features: ONE MICROPHONE BIASING OUTPUT REMOTE CONTROL (REMOCON) FUNCTION THREE SWITCHABLE MICROPHONE AMPLIFIER INPUTS. GAIN PROGRAMMABLE:0 . . 42.5 dB AMPLIFIER, 1.5 dB STEPS (+ MUTE). EARPIECE AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS. EXTERNAL AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS. DRIVING CAPABILITY: 140mW OVER 8 TRANSIENT SUPRESSION SIGNAL DURING POWER ON AND DURING AMPLIFIER SWITCHING. INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. ATTENUATION PROGRAMMABLE: 16 dB RANGE, 1 dB STEP. INTERNAL RING, TONE AND DTMF GENERATOR, SINEWAVE OR SQUAREWAVE WAVEFORMS. ATTENUATION PROGRAMMABLE: 27dB RANGE, 3dB STEP. THREE FREQUENCY RANGES: a) 3.9Hz . . . . 996Hz, 3.9Hz STEP b) 7.8Hz . . . . 1992Hz, 7.8Hz STEP c) 15.6Hz . . . . 3984Hz, 15.6Hz STEP PROGRAMMABLE PULSE WIDTH MODULATED BUZZER DRIVER OUTPUT. General Features: SINGLE 2.7V to 3.3V SUPPLY EXTENDED TEMPERATURE RANGE OPERATION (*) -40C to 85C. 1.0W STANDBY POWER (TYP. AT 2.7V). 13mW OPERATING POWER (TYP. AT 2.7V).
March 2004
TSSOP30 ORDERING NUMBER: STW5093

1.8V TO 3.3V CMOS COMPATIBLE DIGITAL INTERFACES. PROGRAMMABLE PCM AND CONTROL INTERFACE MICROWIRE COMPATIBLE.
APPLICATIONS: GSM/DCS1800/PCS1900/JDC DIGITAL CELLULAR TELEPHONES. CDMA CELLULAR TELEPHONES. DECT/CT2/PHS DIGITAL CORDLESS TELEPHONES. BATTERY OPERATED AUDIO FRONT-ENDS FOR DSPs.
(*) Functionality guaranteed in the range - 40C to +85C; Timing and Electrical Specifications are guaranteed in the range - 30C to +85C.
GENERAL DESCRIPTION STW5093 is a high performance low power combined PCM CODEC/FILTER device tailored to implement the audio front-end functions required by low voltage/low power consumption digital cellular terminals. STW5093 offers a number of programmable functions accessed through a serial control channel that easily interfaces to any classical microcontroller. The PCM interface supports both non-delayed (normal and reverse) and delayed frame synchronization modes. STW5093 can be configurated either as a 14-bit linear or as an 8-bit companded PCM coder. Additionally to the CODEC/FILTER function, STW5093 includes a Tone/Ring/DTMF generator, a sidetone generation, and a buzzer driver output.STW5093 fulfills and exceeds D3/D4 and CCITT recommendations and ETSI requirements for digital handset terminals. Main applications include digital mobile phones, as cellular and cordless phones, or any battery powered equipment that requires audio codecs operating at low single supply voltages.
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PIN CONNECTIONS (Top view)
VCC REMOUT REMIN MIC3+ MIC3MBIAS VCCA MIC1+ MIC1GNDA MIC2+ MIC2VCCP VLrVLr+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D98TL399
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCLK FS DR DX GND CO VCCIO AUXCLK CI CSCCLK BZ LO VFr GNDP
BLOCK DIAGRAM
REMIN MIC PREAMP 0/20dB + MUTE PG DE (A) MIC2+ MIC1+ MIC3+ EARA OUTPUT HPB MIC AMP 0 -> 22.5 1.5dB STEP
REN,RLM,ROI,RDL
REMOCON
REMOUT
MIC3MIC2MIC1-
TX FILTER
PCM ADC
TRANSMIT REGISTER
EN
DX
VS & TE
0 -> -30dB, 2dB STEP
(B)
RX FILTER
PCM DAC
RECEIVE REGISTER
DR
VFr
6dB
OE VLr-1
RTE SE
TONE, RING & DTMF GENER. & FILTER
TONE AMP 0 -> -27dB 3dB STEP
CO
CONTROL INTERFACE -WIRE
SLC
CI CSCCLK MCLK
12dB VLr+
1
SI
EXTA OUTPUT
CLOCK GENERATOR & SYNCHRONIZER
AUX CLK FS
MBIAS
MICROPHONE BIAS
SIDETONE AMP -12.5 -> -27.5dB 1dB STEP BE
INTERFACE LATCH
LO
MB
BUZZER DRIVER
LEVEL ADJUST (PWM)
BZ
D98TL408
GNDP
GNDA
GND
VCCA
VCC
VCCP
VCCIO
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PIN FUNCTION
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14,15 Pin VCC Power supply input for the digital section. Description
REMOUT Remocon function digital output. REMIN MIC3+ MIC3MBIAS VCCA MIC1+ MIC1GNDA MIC2+ MIC2VCCP VLr-, VLr+ Remocon function input. An high level at this pin is detected as a non pressed key, while a low level is detected as a pressed key. Third positive high impedance input to transmit preamplifier for microphone connection. Third negative high impedance input to transmit preamplifier for microphone connection. Microphone Biasing Switch. Power supply input for the analog section. VCC and VCCA can be directly connected together for low cost applications (see STW5093 Power Supply Notes). Positive high impedance input to transmit pre-amplifier for microphone connection. Negative high impedance input to transmit pre-amplifier for microphone connection. Analog Ground: All analog signals are referenced to this pin. GND and GNDA can be connected together for low cost applications (see STW5093 Power Supply Notes). Second Positive high impedance input to transmit pre-amplifier for microphone connection. Second negative high impedance input to transmit pre-amplifier for microphone connection. Power supply input for the VFr and VLr drivers. VCCP and VCCA must be connected together. Receive analog extra amplifier complementary outputs. These outputs can drive directly earpiece transductor of 8 or 50nF. The signal at these outputs can be the sum of: - Receive Speech signal from DR, - Internal Tone generator, - Sidetone signal. Power ground. VFr and VLr drivers are referenced to this pin. GNDP and GNDA must be connected together. Receive analog earpiece amplifier output. This output can drive directly earpiece transductor of 30 or 50nF. The signal at this output can be the sum of: - Receive Speech signal from DR, - Internal Tone Generator, - Sidetone signal. A logic 1 written into DO (CR1) appears at LO pin as a logic 0 A logic 0 written into DO (CR1) appears at LO pin as a logic 1. Pulse width modulated buzzer driver output. Control Clock input: This clock shifts serial control information into CI and out from CO when the CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. Chip Select input: When this pin is low, control information is written into and out from the STW5093 via CI and CO pins. Control data Input: Serial Control information is shifted into the STW5093 on this pin when CS- is low on the rising edges of CCLK.
16 17
GNDP VFr
18 19 20
LO BZ CCLK
21 22 23
CSCI
AUXCLK Auxiliary Clock Input. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CR0. AUXCLK is not used to shift in and out data
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PIN FUNCTION (continued)
N 24 25 26 27 Pin VCCIO CO GND DX Power supply Input for the Digital I/O's. Control data Output: Serial control/status information is shifted out from the STW5093 on this pin when CS- is low on the falling edges of CCLK. Ground: All digital signals are referenced to this pin. Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots. Elsewhere DX output is in the high impedance state. In delayed and non-delayed normal frame synchr. modes, voice data byte is shifted out from TRISTATE output DX at the MCLK on the rising edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted out on the falling edge of MCLK. Receive data input: Data is shifted in during the assigned Received time slots In delayed and non-delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK, while in non-delayed reverse frame synchr. mode voice data byte is shifted in at the MCLK frequency on the rising edges of MCLK. Frame Sync input: This signal is a 8kHz clock which defines the start of the transmit and receive frames. Any of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CR0. MCLK is used also to shift-in and out data. Description
28
DR
29
FS
30
MCLK
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1.0 FUNCTIONAL DESCRIPTION 1.1 DEVICE OPERATION 1.1.1 Power on initialization: When power is first applied, power on reset circuitry initializes STW5093 and puts it into the power down state. Gain Control Registers for the various programmable gain amplifiers and programmable switches are initialized as indicated in the Control Register description section. All CODEC functions are disabled. The desired selection for all programmable functions may be intialized prior to a power up command using the MICROWIRE control channel. Note: after register programming, a subsequent activation of the internal Power on Reset can be detected by programming to 1 the DO bit in the CR1 register; this sets to the logic level 0 the LO output. If an internal Power on Reset occurs, LO automatically switches to logic level 1. 1.1.2 Power up/down control: Following power-on initialization, power up and power down control may be accomplished by writing any of the control instructions listed in Table 1 into STW5093 with "P" bit set to 0 for power up or 1 for power down. Normally, it is recommended that all programmable functions be initially programmed while the device is powered down. Power state control can then be included with the last programming instruction or in a separate single byte instruction. Any of the programmable registers may also be modified while STW5093 is powered up or down by setting "P" bit as indicated. When power up or down control is entered as a single byte instruction, bit 1 must be set to a 0. When a power up command is given, all de-activated circuits are activated, but output DX will remain in the high impedance state until the second Fs pulse after power up. 1.1.3 Power down state: Following a period of activity, power down state may be reentered by writing a power down instruction. Control Registers remain in their current state and can be changed by MICROWIRE control interface. In addition to the power down instruction, detection of loss MCLK (no transition detected) automatically enters the device in "reset" power down state with DX output in the high impedance state. 1.1.4 Transmit section: Transmit analog interface is designed in two stages to enable gains up to 42.5 dB to be realized. Stage 1 is a low noise differential amplifier providing a selectable 0 or 20 dB gain via bit 1 (PG) of register CR4. A microphone may be capacitevely connected to MIC1+, MIC1- inputs, while the MIC2+ MIC2A and MIC3+ MIC3- inputs may be used to capacitively connect a second microphone or a third microphone respectively or an auxiliary audio circuit. MIC1 or MIC2 or MC3 or transmit mute is selected with bits 6 and 7 of register CR4. In the mute case, the analog transmit signal is grounded and the sidetone path is also disabled. Following the first stage is a programmable gain amplifier which provides from 0 to 22.5 dB of additional gain in 1.5dB step. The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the internal 0 dBm0 voltage is 0.49 Vrms (overload level is 0.7 Vrms). Second stage amplifier gain can be programmed with bits 4 to 7 of CR5. An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter can be either a 14-bit linear (bit CM = 0 in register CR0) or can have a compressing characteristics (bit CM = 1 in register CR0) according to CCITT A or MU255 coding laws. A precision on chip voltage reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an internal autozero circuit. Each encode cycle begins immediatly at the beginning of the selected Transmit time slot. The total signal delay referenced to the start of the time slot is approximatively 195 s (due to the transmit filter) plus 125 s (due to encoding delay), which totals 320 s. Voice data is shifted out on DX during the selected time slot on the trans-
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mit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-delayed reverse mode.A separate MBIAS output can be used to bias a microphone (bit MB = 1 in register CR10) 1.1.5 Receive section: Voice Data is shifted into the decoder's Receive voice data Register via the DR pin during the selected time slot on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MCLK in nondelayed reverse mode. The decoder consists of either a 14-bit linear or an expanding DAC with A or MU255 law decoding characteristic. Following the Decoder is a 3400 Hz 8th order band-pass switched capacitor filter with integral Sin X/X correction for the 8 kHz sample and hold. 0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A transcient suppressing circuitry ensure interference noise suppression at power up. The analog speech signal output can be routedeither to earpiece (VFR output) or to an extra analog output (VLr+, VLr- outputs) by setting bits OE1, OE2, and SE (4, 3, and 0 of CR4). Total signal delay is approximatively 190s (filter plus decoding delay) plus 62.5s (1/2 frame) which gives approximatively 252s. Output VFR is intended to directly drive an earpiece. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 4 to 7 in register CR6. Attenuations in the range 0 to -30 dB relative to the maximum level in 2 dB step can be programmed. The input of this programmable amplifier is the sum of several signals which can be selected by writing to register CR4.: - Receive speech signal which has been decoded and filtered, - Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5 VFr is capable of driving output power levels up to 16.5mW into a 30 load impedance capacitively connected between VFr+ and GND. Piezoceramic receivers up to 50nF can also be driven. Differential outputs VLr+,VLr- are intended to directly drive an extra output. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range 0 to -30 dB relative to the maximum level in 2.0 dB step can be programmed. The input of this programmable amplifier can be the sum of signals which can be selected by writing to register CR4: - Receive speech signal which has been decoded and filtered, - Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5. VLr+ and VLr- outputs are capable of driving output power level up to140mW into differentially connected load impedance of 8 . Piezoceramic receivers up to 50nF can also be driven. BUZZER OUTPUT: Single ended output BZ is intended to drive a buzzer, via an external BJT, with a squarewave pulse width modulated (PWM) signal the frequency of which is stored into register CR8. For some applications it is also possible to amplitude modulate this PWM signal with a squarewave signal having a frequency stored in register CR9. Maximum load for BZ is 5k and 50pF. 1.1.6 Digital Interface (Fig. 1) FS Frame Sync input determines the beginning of frame. It may have any duration from a single cycle of MCLK to a squarewave. Three different relationships may be established between the Frame Sync input and the first time slot of frame by setting bits DM1 and DM0 in register CR1. In non delayed data mode (long frame timing) the first time slot begins nominally coincident with the rising edge of FS. Alternative is to use delayed data mode (short frame sync timing) in which FS input must be high at least a half cycle of MCLK earlier the frame beginning In the case of linear code (bit CM = 0 in register CR0) the MSB is the first bit that is transmitted and received.
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In the case of companded code only (bit CM = 1 in register CR0) a time slot assignment circuit on chip may be used with all timing modes, allowing connection to one of the two B1 and B2 voice data channels. Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles following immediately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles following immediately time slot B1. In Format 2, time slot B1 is identical to Format 1. Time slot B2 appears two bit slots after time slot B1. This two bits space is left available for insertion of the D channel data. Data format is selected by bit FF (2) in register CR0. Time slot B1 or B2 is selected by bit TS (1) in Control Register CR1. Bit EN (2) in control register CR1 enables or disables the voice data transfer on DX and DR as appropriate. During the assigned time slot, DX output shifts data out from the voice data register on the rising edges of MCLK in the case of delayed and non-delayed normal modes or on the falling edges of MCLK in the case of non-delayed reverse mode. Serial voice data is shifted into DR input during the same time slot on the falling edges of MCLK in the case of delayed and non-delayed normal modes or on the rising edges of MCLK in the case of nondelayed reverse mode. DX is in the high impedance Tristate condition when in the non selected time slots. Figure 1. Digital Interface Format (significant only for companded code)
FORMAT 1
FS (delayed timing)
FS
(non delayed timing)
MCLK
DR
B1
B2
X
X
X
DX
B1
B2
FORMAT 2
FS (delayed timing)
FS
(non delayed timing)
MCLK
DR
B1
X
B2
X
X
DX
B1
B2
D98TL394
1.1.7 Control Interface: Control information or data is written into or read-back from STW5093 via the serial control port consisting of control clock CCLK, serial data input CI and output CO, and Chip Select input, CS-. All control instructions require 2 bytes as listed in Table 1, with the exception of a single byte power-up/down command. To shift control data into STW5093, CCLK must be pulsed high 8 times while CS- is low. Data on CI input is shifted into the serial input register on the rising edge of each CCLK pulse. After all data is shifted in, the content of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be defined by a second byte-wide CS- pulse or may follow the first contiguously, i.e. it is not mandatory for CS- to return high in between the first and second control bytes. At the end of the 2nd control byte, data is loaded into the appropriate programmable register. CS- must return high at the end of the 2nd byte.
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To read-back status information from STW5093, the first byte of the appropriate instruction is strobed in during the first CS- pulse, as defined in Table 1. CS- must be set low for a further 8 CCLK cycles, during which data is shifted out of the CO pin on the falling edges of CCLK. When CS- is high, CO pin is in the high impedance Tri-state, enabling CO pins of several devices to be multiplexed together. Thus, to summarise, 2 byte READ and WRITE instructions may use either two 8-bit wide CS- pulses or a single 16 bit wide CS- pulse. 1.1.8 Control channel access to PCM interface: It is possible to access the B channel previously selected in Register CR1 in the case of companded code only. A byte written into Control Register CR3 will be automatically transmitted from DX output in the following frame in place of the transmit PCM data. A byte written into Control Register CR2 will beautomatically sent through the receive path to the Receive amplifiers. In order to implement a continuous data flow from the Control MICROWIRE interface to a B channel, it is necessary to send the control byte on each PCM frame. A current byte received on DR input can be read in the register CR2. In order to implement a continuous data flow from a B channel to MICROWIRE interface, it is necessary to read register CR2 at each PCM frame. 1.1.9 AUXCLK usage: The Auxiliary clock AUXCLK is only used to keep active the tone and buzzer generation functions to the Earpiece or to the Extra amplifier outputs when the Master Clock MCLK is not available, and there is no voice activity both in transmit and receive channels. When AUXCLK is selected, the PCM digital interface is inactive (DX in tristate and DR is not read). The selection between AUXCLK and MCLK is done by bit SLC in register CR1The input frequency of AUXCLK is selected via bits F1 and F0 of register CR0 as for the MCLK signal. 1.1.10REMOCON function: The REMOCON (Remote Control) function can be used to detect the status of an headset button. The REMOCON function is enabled by setting bit REN (7 of CR10). If enabled, this function is active also when the STW5093 is in Power-down state. At REMIN input an high level is detected as a non pressed button, while a low level is detected as a pressed button. The "Pressed Button" information can be treated in 2 ways depending on bit RLM (6 of CR10): if RLM = 0 (Transparent mode) the information at REMIN is seen at REMOUT after a debounce time of 50ms maximum. if RLM = 1 (Latched Mode) the information stored in bit RDL (4 of CR10) is seen at REMOUT.When a low level at REMIN is detected RDL is set after a debounce time of 50ms maximum.RDL is reset at power on reset and can also be reset writing CR10. The REMOUT output polarity can be inverted setting bit ROI (5 of CR10):the pressed button information is presented at REMOUT output as a logic 1 if bit ROI = 0. If ROI = 1 the polarity is inverted. 2.0 PROGRAMMABLE FUNCTIONS The programmable functions are configured by writing to a number of registers using a 2-byte write cycle. Most of these registers can also be read-back for verification. Byte one is always register address, while byte two is Data. Table 1 lists the register set and their respective adresses.
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Table 1. Programmable Register Intructions
Address byte Function 7 Single byte Power up/down Write CR0 Read-back CR0 Write CR1 Read-back CR1 Write Data to receive path Read data from DR Write Data to DX Write CR4 Read-back CR4 Write CR5 Read-back CR5 Write CR6 Read-back CR6 Write CR7 Read-back CR7 Write CR8 Read-back CR8 Write CR9 Read-back CR9 Write CR10 Read-back CR10 Write CR11 Read-back CR11 Write Test Register CR12 Write Test Register CR13 Write Test Register CR14 P P P P P P P P P P P P P P P P P P P P P P P P P P P 6 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 5 X 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 4 X 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 3 X 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 2 X 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X none see CR0 TABLE 2 see CR0 see CR1 TABLE 3 see CR1 see CR2 TABLE 4 see CR2 see CR3 TABLE 5 see CR4 TABLE 6 see CR4 see CR5 TABLE 7 see CR5 see CR6 TABLE 8 see CR6 see CR7 TABLE 9 see CR7 see CR8 TABLE 10 see CR8 see CR9 TABLE 11 see CR9 see CR10 TABLE 12 see CR10 see CR11 TABLE 13 see CR11 reserved reserved reserved Data byte
Notes: 1. bit 7 of the address byte and data byte is always the first bit clocked into or out from: CI and CO pins when MICROWIRE serial port is enabled. X = reserved: write 0 2. "P" bit is Power up/down Control bit. P = 1 Means Power Down.Bit 1 indicates, if set, the presence of a second byte. 3. Bit 2 is write/read select bit. 4. Registers CR12, CR13, and CR14 are not accessible.
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Table 2. Control Register CR0 Functions
7 F1 0 0 1 1 6 F0 0 1 0 1 0 1 5 CM 4 MA 3 IA 2 FF 1 B7 0 Function DL MCLK or AUXCLK = 512 kHz MCLK or AUXCLK = 1.536 MHz MCLK or AUXCLK = 2.048 MHz MCLK or AUXCLK = 2.560 MHz Linear code Companded code Linear Code 0 0 1 1 0 1 0 1 0 1 0 1 0 1
*: (1): state at power on initialization significant in companded mode only
*
* Companed Code MU-law: CCITT D3-D4 * MU-law: Bare Coding A-law including even bit inversion A-law: Bare Coding * * * * (1) (1) (1) (1)
2-complement * sign and magnitude 2-complement 1-complement B1 and B2 consecutive B1 and B2 separated 8 bits time-slot 7 bits time-slot Normal operation Digital Loop-back
Table 3. Control Register CR1 Functions
7 DM1 0 1 1 6 DM0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1
*: (1): X: state at power on initialization significant in companded mode only reserved: write 0
5 DO
4 MR
3 MX
2 EN
1 TS
0 Function SLC delayed data timing non-delayed normal data timing non-delayed reverse data timing L0 latch set to 1 L0 latch set to 0 DR connected to rec. path CR2 connected to rec. path Trans path connected to DX CR3 connected to DX voice data transfer disable voice data transfer enable B1 channel selected B2 channel selected *
* * (1) * (1) * * (1)
MCLK Master Clock and FS Frame Sync inputs are selected * AUXCLK Auxiliary Clock input is selected
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Table 4. Control Register CR2 Functions
7 d7 msb
(1) Significant in companded mode only.
6 d6
5 d5
4 d4
3 d3
2 d2
1 d1
0 Function d0 lsb Data sent to Receive path or Data received from DR input (1)
Table 5. Control Registers CR3 Functions
7 d7 msb
(1) Significant in companded mode only.
6 d6
5 d5
4 d4
3 d3
2 d2
1 d1
0 Function d0 lsb DX data transmitted (1)
Table 6. Control Register CR4 Functions
7 VS 0 0 1 1 6 TE 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
*: state at power on initialization
5 SI
4 OE1
3 OE2
2 RTE
1 HPB
0 Function SE Transmit input muted MIC1 Selected MIC2 Selected MIC3 Selected Internal sidetone disabled Internal sidetone enabled Receive output muted VFr output selected VLr output selected NOT ALLOWED Ring / Tone to VFr or VLr disabled Ring / Tone to VFr or VLr enabled Receive High Pass filter enabled Receive High Pass filter disabled Receive Signal to VFr or VLr disabled Receive Signal to VFr or VLr enabled *
* *
*
* *
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Table 7. Control Register CR5 Functions
7 6 5 4 3 2 1 0 Function Transmit amplifier 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1
*: state at power on initialization
Sidetone amplifier lsb 0 dB gain 1.5 dB gain in 1.5 dB step 22.5 dB gain -12.5 dB gain -13.5 dB gain in 1 dB step -27.5 dB gain *
0 0 1
0 0 1
0 1 1
*
Table 8. Control Register CR6 Functions
7 6 5 4 3 2 1 0 Function Extra amplifier [EXTA] 0 1 1 0 0 1
*: state at power on initialization
Earpiece ampifier [EARA] 0 0 1 0 0 1 0 0 1
lsb
0 dB gain -2 dB gain in 2 dB step -30 dB gain 0 dB gain -2 dB gain in 2 dB step -30 dB gain
*
0 0 1
0 0 1
0 1 1
*
Table 9. Control Register CR7 Functions
7 6 5 4 3 F1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1
*: (2): X
2 F2
1 SN
0 DE Attenuation 0 dB * -3 dB -6 dB - 9 dB -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB
Function f1 VPP 1.6(2) f2 VPP 1.26(2)
Tone gain 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 X X
0.066
0.053 *
f1 and f2 muted f2 selected f1 selected f1 and f2 in summed mode Squarewave signal selected Sinewave signal selected Normal operation Tone / Ring Generator connected toTransmit path
*
*
state at power on initialization value provided if f1 or f2 is selected alone.if f1 and f2 are selected in the summed mode, f1=0.89 Vpp while f2=0.7 Vpp. reserved: write 0
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Table 10. Control Register CR8 Functions
7 f17 msb 6 f16 5 f15 4 f14 3 f13 2 f12 1 f11 0 Function f10 lsb Binary equivalent of the decimal number used to calculate f1
Table 11. Control Register CR9 Functions
7 f27 msb 6 f26 5 f25 4 f24 3 f23 2 f22 1 f21 0 Function f20 lsb Binary equivalent of the decimal number used to calculate f2
Table 12. Control Register CR10 Functions
7 6 5 ROI 4 RDL 3 PG 2 MB 1 DFT 0 Function REN RLM 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1
(*) Default values inserted into the Register at Power On.
HFT Remocon Function disabled Remocon Function enabled Remocon output in transparent mode Remocon output in latched mode Remocon output not inverted Remocon output inverted Remocon detection latch reset by P Remocon detection latch set by internal logic 20dB preamplifier gain 0dB preamplifier gain MBIAS output disabled MBIAS output enabled 0 1 0 1 Standard Frequency Tone Range Halved Frequency Tone Range Doubled Frequency Tone Range Forbidden * * * * * * *
Table 13. Control Register CR11 Functions
7 BE 0 1 0 1 msb
* state at power on initialization
6 BI
5 BZ5
4 BZ4
3 BZ3
2 BZ2
1 BZ1
0 Function BZ0 Buzzer output disabled (set to 0) Buzzer output enabled * *
Duty Cycle is intended as the relative width of logic 1 Duty cycle is intended as the relative width of logic 0 lsb
Binary equivalent of the decimal number used to calculate the duty cycle.
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CONTROL REGISTER CR0 First byte of a READ or a WRITE instruction to Control Register CR0 is as shown in TABLE 1. Second byte is as shown in TABLE 2. Master Clock / Auxiliary Clock Frequency Selection A master clock must be provided to STW5093 to activate all the functions. In the case MCLK is absent, AUXCLK can be provide to STW5093 for activating tone or buzzer functions only. MCLK or AUXCLK frequency can be either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz.. Bit F1 (7) and F0 (6) must be set during initialization to select the correct internal divider.Default value is 512 kHz. Any clock different from the default one must be selected prior a Power-Up instruction. Coding Law Selection Bits MA (4) and IA (3) permit selection of Mu-255 law or A law coding with or without even bit inversion if companded code (bit CM = 1) is selected. Bits MA(4) and IA(3) permit selection of 2-complement, 1-complement or sign and magnitude if linear code (bit CM = 0) is selected. Coding Selection Bit CM (5) permits selection either of linear coding (14-bit) or companded coding (8-bit). Default value is linear coding. Digital Interface format (1) Bit FF(2) = 0 selects digital interface in Format 1 where B1 and B2 channel are consecutive. FF=1 selects Format 2 where B1 and B2 channel are separated by two bits. (See digital interface format section.) 56+8 selection (1) Bit 'B7' (1) selects capability for STW5093 to take into account only the seven most significant bits of the PCM data byte selected. When 'B7' is set, the LSB bit on DR is ignored and LSB bit on DX is high impedance. This function allows connection of an external "in band" data generator directly connected on the Digital Interface. Digital loopback Digital loopback mode is entered by setting DL bit(0) equal 1. In Digital Loopback mode, data written into Receive PCM Data Register from the selected received time-slot is read-back from that Register in the selected transmit time-slot on DX. No PCM decoding or encoding takes place in this mode. Transmit and Receive amplifier stages are muted. CONTROL REGISTER CR1 First byte of a READ or a WRITE instruction to Control Register CR1 is as shown in TABLE 1. Second byte is as shown in TABLE 3. Digital Interface Timing Bit DM1(7) = 0 selects digital interface in delayed timing mode, while DM1 = 1 and DM0 = 0 selects non-delayed normal data timing mode, and DM1 = 1 and DM0 = 1 selects non-delayed reverse data timing mode.Default is delayed data timing.
(1) Significant in companded mode only
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Latch output control Bit DO controls directly logical status of latch output LO: ie, a "ZERO" written in bit DO puts the output LO at logical 1, while a "ONE" written in bit DO sets the output LO to zero. Microwire access to B channel on receive path (1) Bit MR (4) selects access from MICROWIRE Register CR2 to Receive path. When bit MR is set high, data written to register CR2 is decoded each frame, sent to the receive path and data input at DR is ignored. In the other direction, current PCM data input received at DR can be read from register CR2 each frame. Microwire access to B channel on transmit path (1) Bit MX (3) selects access from MICROWIRE write only Register CR3 to DX output. When bit MX is set high, data written to CR3 is output at DX every frame and the output of PCM encoder is ignored.
True A law even bit inversion lsb 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 msb 1 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 lsb 0 1 1 0 A law without even bit inversion msb 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 lsb 1 0 0 1
Mu 255 law msb Vin = + full scale Vin = 0V Vin = - full scale 1 1 0 0 0 1 1 0
MSB is always the first PCM bit shifted in or out of: STW5093.
Transmit/Receive enabling/disabling Bit 'EN' (2) enables or disables voice data transfer on DX and DR pins. When disabled, PCM data from DR is not decoded and PCM time-slots are high impedance on DX. Default value is disabled. B-channel selection (1) Bit TS(1) permits selection between B1 or B2 channels. Default value is B1 channel. Clock Selection Bit SLC(0) allows the selection between MCLK and AUXCLK. Default value is MCLK. CONTROL REGISTER CR2(1) Data sent to receive path or data received from DR input. Refer to bit MR(4) in "Control Register CR1" paragraph. CONTROL REGISTER CR3 (1) DX data transmitted. Refer to bit MX(3) in "Control Register CR1" paragraph. CONTROL REGISTER CR4 First byte of a READ or a WRITE instruction to Control Register CR4 is as shown in TABLE 1. Second byte is as shown in TABLE 6.
(1) Significant in companded mode only
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Transmit Input Selection MIC1 or MIC2 or MIC3 or transmit mute can be selected with bits 6 and 7 (VS and TE). Transmit gain can be adjusted within a 22.5 dB range in 1.5 dB step with Register CR5. Sidetone Selection Bit "SI" (5) enables or disables Sidetone circuitry. When enabled, sidetone gain can be adjusted with Register (CR5). When Transmit path is disabled, sidetone circuit is also disabled. Output Driver Selection Bits OE1(4) and OE2(3) provide the selection among the earpiece output or the extra amplifier output or both outputs muted.OE1 = 1 and OE2 = 1 is not allowed. Ring/Tone signal selection Bit RTE (2) provide select capability to connect on-chip Ring/Tone generator either to an extra amplifier input or to earpiece amplifier input. Receiver High Pass Filter Selection Bit HPB(1) provides the selection of the receiver high pass filter cutoff frequency. PCM receive data selection Bits "SE" (0) provide select capability to connect received speech signal either to an extra amplifier input or to earpiece amplifier input.
CONTROL REGISTER CR5 First byte of a READ or a WRITE instuction to Control Register CR5 is as shown in TABLE 1. Second byte is as shown in TABLE 7. Transmit gain selection Transmit amplifier can be programmed for a gain from 0dB to 22.5dB in 1.5dB step with bits 4 to 7. 0 dBmO level at the output of the transmit amplifier (A reference point) is 0.492 Vrms (overload voltage is 0.707 Vrms). Sidetone attenuation selection Transmit signal picked up after the switched capacitor low pass filter may be fed back into both Receive amplifiers. Attenuation of the signal at the output of the sidetone attenuator can be programmed from A12.5dB to -27.5dB relative to reference point A in 1 dB step with bits 0 to 3.
CONTROL REGISTER CR6 First byte of a READ or a WRITE instruction to Control Register CR6 is as shown in TABLE 1. Second byte is as shown in TABLE 8.
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Earpiece amplifier gain selection: Earpiece Receive gain can be programmed in 2 dB step from 0 dB to -30 dB relative to the maximum with bits 4 to 7. 0 dBmO voltage at the output of the amplifier on pin VFr is 0.9825 Vrms when 0dB gain is selected down to 30.925 Vrms when -30dB gain is selected. Extra amplifier gain selection: Extra Receive amplifier gain can be programmed in 2 dB step from 0 dB to -30 dB relative to the maximum with bits 0 to 3. 0 dBmO voltage on the output of the amplifier on pins VLr+ and VLr- 1.965 Vrms when 0 dB gain is selected down to 61.85 mVrms when -30 dB gain is selected.
CONTROL REGISTER CR7: First byte of a READ or a WRITE instruction to Control Register CR7 is as shown in TABLE 1. Second byte is as shown in TABLE 9. Tone/Ring amplifier gain selection Output level of Ring/Tone generator, before attenuation by programmable attenuator is 1.6 Vpk-pk when f1 generator is selected alone or summed with the f2 generator and 1.26 Vpk-pk when f2 generator is selected alone. Selected output level can be attenuated down to -27 dB by programmable attenutator by setting bits 4 to 7. Frequency mode selection Bits 'F1' (3) and 'F2' (2) permit selection of f1 and/or f2 frequency generator according to TABLE 9. When f1 (or f2) is selected, output of the Ring/Tone is a squarewave (or a sinewave) signal at the frequency selected in the CR8 (or CR9) Register. When f1 and f2 are selected in summed mode, output of the Ring/Tone generator is a signal where f1 and f2 frequency are summed. In order to meet DTMF specifications, f2 output level is attenuated by 2dB relative to the f1 output level. Frequency temporization must be controlled by the microcontroller. Waveform selection Bit 'SN' (1) selects waveform of the output of the Ring/Tone generator. Sinewave or squarewave signal can be selected. DTMF selection Bit DE (0) permits connection of Ring/Tone/DTMF generator on the Transmit Data path instead of the Transmit Amplifier output. Earpiece or extra receive output feed-back may be provided by sidetone circuitry by setting bit SI or directly by setting bit RTE in Register CR4. Loudspeaker feed-back may be provided directly by setting bit RTL in Register CR4.
CONTROL REGISTERS CR8 AND CR9 First byte of a READ or a WRITE instruction to Control Register CR8 or CR9 is as shown in TABLE 1. Second byte is respectively as shown in TABLE 10 and 11. If "standard frequency tone range" is selected, Tone or Ring signal frequency value is defined by the formula: f1 = CR8 / 0.128 Hz
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and f2 = CR9 / 0.128 Hz where CR8 and CR9 are decimal equivalents of the binary values of the CR8 and CR9 registers respectively. Thus, any frequency between 7.8 Hz and 1992 Hz may be selected in 7.8 Hz step. If "halved frequency tone range"is selected, Tone or Ring signal frequency value is defined by the formula: f1 = CR8 / 0.256 Hz and f2 = CR9 / 0.256 Hz This any frequency between 3.9Hz and 996Hz may be selected in 3.9Hz step. If "doubled frequency tone range"is selected, Tone or Ring signal frequency value is defined by the formula: f1 = CR8 / 0.064 Hz and f2 = CR9 / 0.064 Hz Thus any frequency between 15.6Hz and 3984Hz may be selected in 15.6Hz step. TABLE 12 gives examples for the main frequencies usual for Tone or Ring generation.
CONTROL REGISTER CR10 Remocon Function Enable Bit REN(7) enables or disables the RemoconFunction. Default value is disabled. Remocon Mode Selection Bit RLM(6) is used to select between a transparent pressed button information and a latched pressed button information at REMOUT. In both cases a debounce circuit (50ms max.) is active. Remocon Output Inversion Bit ROI(5) is used to invert or not the information at REMOUT. Default value is not inverted (i.e. pressed button information is a logic 1 at REMOUT. Remocon Detection Latch Bit RDL(4) is set by the internal Remocon Function logic, after the debounce time, when a low level on REMIN is detected. It can be reset by the mP writing CR10. Preamplifier Gain Selection Bit PG(3) provides the selection between 0dB and 20dB gain of the preamplifier. Default value is 20dB. Microphone Bias Disabling/Enabling Bit MB (2) enables or disables a switch for microphone biasing. Default value is disabled. Tone Frequency Range Selection Bit DFT(1) and HFT(0) permits the selection among "standard frequency tone range" (i.e. from 7.8Hz to 1992Hz in 7.8Hz step), "halved frequency tone range" (i.e. from 3.9Hz to 996Hz in 3.9Hz step), and "doubled frequency
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tone range" (i.e. from 15.6Hz to 3984Hz in 15.6Hz step) according to the values described in CONTROL REGISTER CR8 and CR9.
CONTROL REGISTER CR11 Bit BE(7) permits connection of a f1 squarewave PWM Ring signal, amplitude modulated or not by a f2 squarewave signal, to buzzer driver output BZ. Bits BZ5 to BZ0 define the duty cycle of the PWM squarewave, according to the following formula: Duty Cycle = CR11(5 to 0) x 0.78125% where CR11(5 to 0) is the decimal equivalent of the binary value BZ5 to BZ0. When BE = 1, if bits F1 = 1 and F2 = 0 in register CR7, a f1 PWM ring signal is present at the buzzer output, while if bits F1 = 1 and F2 = 1 in register CR7 the f1 PWM ring signal is also amplitude modulated by a f2 squarewave frequency. Bit BI (6) allows to chose the logic level at which the duty cycle is referred: BI = 0 means that duty cycle is intended as the relative width of the logic1, while BI = 1 means that duty cycle is intended as the relative width of the logic 0. When BE = 0 (or during power down) BZ = 0 if BI = 0 or BZ = 1 if BI = 1.
Table 14. Examples of Usual Frequency Selection (Standard frequency tone range)
Description Tone 250 Hz Tone 330 Hz Tone 425 Hz Tone 440 Hz Tone 800 Hz Tone 1330 Hz DTMF 697Hz DTMF 770 Hz DTMF 852 Hz DTMF 941 Hz DTMF 1209 Hz DTMF 1336 Hz DTMF 1477 Hz DTMF 1633 Hz SOL LA SI DO RE MI flat MI FA FA sharp SOL SOL sharp LA SI DO RE MI f1 value (decimal) 32 42 54 56 102 170 89 99 109 120 155 171 189 209 50 56 63 67 75 80 84 89 95 100 106 113 126 134 150 169 Theoretic value (Hz) 250 330 425 440 800 1330 697 770 852 941 1209 1336 1477 1633 392 440 494 523.25 587.33 622.25 659.25 698.5 740 784 830.6 880 987.8 1046.5 1174.66 1318.5 Typical value (Hz) 250 328.2 421.9 437.5 796.9 1328.1 695.3 773.4 851.6 937.5 1210.9 1335.9 1476.6 1632.8 390.6 437.5 492.2 523.5 586.0 625.0 656.3 695.3 742.2 781.3 828.2 882.9 984.4 1046.9 1171.9 1320.4 Error% -.00 -.56 -.73 -.56 -.39 -.14 -.24 +.44 -.05 -.37 +.16 -.01 .00 .00 -.30 -.56 -.34 +.04 -.23 +.45 -.45 -.45 +.30 -.34 -.29 +.33 -.34 +.04 -.23 +.14
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TIMING DIAGRAM Figure 2. Non Delayed Data Timing Mode (Normal) (*)
Figure 3. Delayed Data Timing Mode (*)
(*) In the case of companded code the timing is applied to 8 bits instead of 16 bits.
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TIMING DIAGRAM Figure 4. Non Delayed Reverse Data Timing Mode (*
tHMFR
tRM
tFM
tWMM
MCLK
1 tSFMR tHMFR
2
3
4
5
6
7
16
17
tWML
FS
tDFD tDMDR tDMZR
DX
1
2 tSDM
3 tHMDR
4
5
6
7
16
DR
1
2
3
4
5
6
7
16
D93TL076A
(*) In the case of companded code the timing is applied to 8 bits instead of 16 bits.
Figure 5. Serial Control Timing (MICROWIRE MODE)
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ABSOLUTE MAXIMUM RATINGS
Parameter VCC to GND Voltage at MIC (VCC 3.3V) Current at VFr and VLr Current at any digital output Voltage at any digital input (VCCIO 3.3V); limited at 50mA Storage temperature range Lead Temperature (wave soldering, 10s) Value 4.6 VCC +0.5 to GND -0.5 100 50 VCCIO + 0.5 to GND -0.5 - 65 to + 150 + 260 Unit V V mA mA V C C
OPERATIVE SUPPLY VOLTAGES
Symbol VCC = VCCA = VCCP VCCIO Min. 2.7 1.8 Max. 3.3 VCC Unit V V
TIMING SPECIFICATIONS (unless otherwise specified, VCCIO = 1.8V to 3.3V ,Tamb = -30C to 85C ; typical characteristics are specified at VCCIO = 3.0V, Tamb = 25 C; all signals are referenced to GND, see Note 5 for timing definitions) NOTICE: All timing specifications can be changed. MASTER CLOCK TIMING
Symbol Parameter Test Condition Selection of frequency is programmable (see table 2) Min. Typ. 512 1.536 2.048 2.560 150 150 30 30 Max. Unit kHz MHz MHz MHz ns ns ns ns
fMCLK
Frequency of MCLK
tWMH tWML tRM tFM
Period of MCLK high Period of MCLK low Rise Time of MCLK Fall Time of MCLK
Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL
PCM INTERFACE TIMING
Symbol tHMF tSFM tDMD Parameter Hold Time MCLK low to FS low Setup Time, FS high to MCLK low Delay Time, MCLK high to data valid Load = 20pF Test Condition Min. 0 30 100 Typ. Max. Unit ns ns ns
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TIMING SPECIFICATIONS (continued) PCM INTERFACE TIMING (continued)
Symbol tDMZ tDFD Parameter Delay Time, MCLK low to DX disabled Delay Time, FS high to data valid Load = 20pF; Applies only if FS rises later than MCLK rising edge in Non Delayed Mode only 20 10 30 30 Load = 20pF 10 20 100 100 Test Condition Min. 10 Typ. Max. 100 100 Unit ns ns
tSDM tHMD tHMFR tSFMR tDMDR tDMZR tHMDR
Setup Time, DR valid to MCLK receive edge Hold Time, MCLK low to DR invalid Hold Time MCLK High to FS low Setup Time, FS high to MCLK High Delay Time, MCLK low to data valid Delay Time, MCLK High to DX disabled Hold Time, MCLK High to DR invalid
ns ns ns ns ns ns ns
SERIAL CONTROL PORT TIMING
Symbol fCCLK tWCH tWCL tRC tFC tHCS tSSC tSDC tHCD tDCD tDSD Parameter Frequency of CCLK Period of CCLK high Period of CCLK low Rise Time of CCLK Fall Time of CCLK Hold Time, CCLK high to CS- low Setup Time, CS- low to CCLK high Setup Time, CI valid to CCLK high Hold Time, CCLK high to CI invalid Delay Time, CCLK low to CO data valid Delay Time, CS-low to CO data valid Load = 20pF Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL 10 50 50 50 80 50 160 160 50 50 Test Condition Min. Typ. Max. 2.048 Unit MHz ns ns ns ns ns ns ns ns ns ns
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TIMING SPECIFICATIONS (continued) SERIAL CONTROL PORT TIMING (continued)
Symbol tDDZ Parameter Delay Time CS-high or 8th CCLK low to CO high impedance whichever comes first Hold Time, 8th CCLK high to CShigh Set up Time, CS- high to CCLK high Test Condition Min. 10 Typ. Max. 80 Unit ns
tHSC tSCS
Note 5:
100 100
ns ns
A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purposes of this specification the following conditions apply: a) All input signal are defined as: VIL = 0.2VCCIO, VIH = 0.8VCCIO, tR < 10ns, tF < 10ns. b) Delay times are measured from the inputs signal valid to the output signal valid. c) Setup times are measured from the data input valid to the clock input invalid. d) Hold times are measured from the clock signal valid to the data input invalid.
ELECTRICAL CHARACTERISTICS (unless otherwise specified, VCCIO = 1.8V to 3.3V, Tamb = -30C to 85C; typical characteristic are specified at VCCIO = 3.0V, Tamb = 25C ; all signals are referenced to GND) DIGITAL INTERFACES
Symbol VIL Parameter Input Low Voltage Test Condition All digital inputs except REMIN DC AC All digital inputs except REMIN DC 0.7VCCIO AC 0.8VCCIO REMIN input REMIN input All digital outputs, IL = 10A All digital outputs, IL = 2mA All digital outputs, IL = 10A All digital outputs, IL = 2mA Any digital input, GND < VIN < VIL Any digital input, VIH < VIN < VCCIO DX and CO VCCIO-0.1 VCCIO-0.4 -10 -10 -10 10 10 10 1.4 0.1 0.4 0.5 Min. Typ. Max. 0.3VCCIO 0.2VCCIO Unit V V
VIH
Input High Voltage
V V V V V V V V A A A
VILREM VIHREM VOL VOH IIL IIH IOZ
Input Low Voltage Input High Voltage Output Low Voltage
Output High Voltage
Input Low Current Input High Current Output Current in High impedance (Tri-state)
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Figure 6. A.C. TESTING INPUT, OUTPUT WAVEFORM
INTPUT/OUTPUT
0.8VCCIO 0.7VCCIO TEST POINTS 0.2VCCIO 0.3VCCIO 0.3VCCIO
D93TL077A
0.7VCCIO
AC Testing: inputs are driven at 0.8VCCIO for a logic "1"and 0.2VCCIO for a logic "0 ". Timing measurements are made at 0.7VCCIO for a logic "1"and 0.3VCCIO for a logic "0".
ANALOG INTERFACES
Symbol RMBIAS IMIC RMIC RLVFr CLVFr ROVFr0 RLvLr CLvLr ROLVrO VOSVLrO Parameter Switch Resistance for Microphone bias Input Leakage Input Resistance Load Resistance Load Capacitance Output Resistance Load Resistance Load Capacitance Output Resistance Differential offset Voltage at VLr+, VLrSteady zero PCM code applied to DR; I = 1mA VLr+ to VLrfrom VLr+ to VLrSteady zero PCM code applied to DR; I 1mA Alternating zero PCM code applied to DR maximum receive gain; RL = 50 -50 8 50 1 +50 Test Condition MBIAS 100mV under VCC GND < VMIC < VCC GND < VMIC < VCC -100 50 30 50 1.0 Min. Typ. Max. 150 +100 Unit A k nF nF mV
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TRANSMISSION CHARACTERISTICS (unless otherwise specified, VCC = 2.7V to 3.3V, Tamb = -30C to 85C; typical characteristics are specified at VCC = 3.0V, Tamb = 25C, MIC1/2/3 = 0dBm0, DR = -6dBm0 PCM code, f = 1015.625 Hz; all signal are referenced to GND) AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Transmit path - Absolute levels at MIC1 / MIC2 / MIC3
Symbol Parameter 0 dBm0 level Overload level 0 dBm0 level Overload level Transmit Amps connected for 42.5dB gain Test Condition Transmit Amps connected for 20dB gain Min. Typ. 49.26 70.71 3.694 5.302 Max. Unit mVRMS mVRMS mVRMS mVRMS
AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Receive path - Absolute levels at VFr
Symbol Parameter 0 dBM0 level 0 dBM0 level Test Condition Receive Amp programmed for 0dB attenuation Receive Amp programmed for30dB attenuation Min. Typ. 0.9825 30.925 Max. Unit VRMS mVRMS
AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Receive path - Absolute levels at VLr (Differentially measured)
Symbol Parameter 0 dBM0 level 0 dBM0 level Test Condition Receive Amp programmed for 0dB attenuation Receive Amp programmed for 30dB attenuation Min. Typ. 1.965 61.85 Max. Unit VRMS mVRMS
AMPLITUDE RESPONSE Transmit path
Symbol GXA Parameter Transmit Gain Absolute Accuracy Test Condition Transmit Gain Programmed for minimum.Measure deviation of Digital PCM Code from ideal 0dBm0 PCM code at DX Measure Transmit Gain over the range from Maximum to minimum setting.Calculate the deviation from the programmed gain relative to GXA, i.e. GAXG = G actual - G prog. - GXA Measured relative to GXA. min. gain < GX < Max. gain Measured relative to GXA GX = Minimum gain Min. -0.5 Typ. Max. 0.5 Unit dB
GXAG
Transmit Gain Variation with programmed gain
-0.5
0.5
dB
GXAT GXAV
Transmit Gain Variation with temperature Transmit Gain Variation with supply
-0.1
0.1
dB
-0.1
0.1
dB
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AMPLITUDE RESPONSE(continued) Transmit path (continued)
Symbol GXAF Parameter Transmit Gain Variation with frequency Test Condition Relative to 1015,625 Hz, multitone test technique used.min. gain < GX < Max. gain f = 60 Hz f = 100 Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz (*) f = 8000 Hz (*) Sinusoidal Test method.Reference Level = -10 dBm0 VMIC = -40 dBm0 to +3 dBm0 VMIC = -50 dBm0 to -40 dBm0 VMIC = -55 dBm0 to -50 dBm0 Min. Typ. Max. Unit
-1.5 -0.5 -1.5
-30 -20 -6 0.5 0.5 0.0 -14 -35 -47
dB dB dB dB dB dB dB dB dB
GXAL
Transmit Gain Variation with signal level
-0.5 -0.5 -1.2
0.5 0.5 1.2
dB dB dB
(*) The limit at frequencies between 4600Hz and 8000Hz lies on a straight line connecting the two frequencies on a linear (dB) scale versus log (Hz) scale.
Receive path
Symbol GRAE Parameter Receive Gain Absolute Accuracy Test Condition Receive gain programmed for maximum Apply -6 dBm0 PCM code to DR Measure VFr Receive gain programmed for maximum Apply -6 dBm0 PCM code to DR Measure VLr Measure VFr Gain over the range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GRAE, i.e. GRAGE = G actual - G prog. - GRAE Measure VLr Gain over the range from Maximum to minimum setting.Calculate the deviation from the programmed gain relative to GRAL, i.e. GRAGL = G actual - G prog. - GRAL Measured relative to GRA. (VLr and VFr) min. gain < GR < Max. gain Min. -0.5 Typ. Max. 0.5 Unit dB
GRAL
Receive Gain Absolute Accuracy
-0.5
0.5
dB
GRAGE
Receive Gain Variation with programmed gain
-0.5
0.5
dB
GRAGL
Receive Gain Variation with programmed gain
-0.5
0.5
dB
GRAT
Receive Gain Variation with temperature
-0.1
0.1
dB
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AMPLITUDE RESPONSE(continued) Receive path (continued)
Symbol GRAV Parameter Receive Gain Variation with Supply Test Condition Measured relative to GRA. (VLr and VFr) GR = Maximum Gain Relative to 1015,625 Hz, multitone test technique used. min. gain < GR < Max. gain f = 60Hz f = 100Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz Relative to 1015,625 Hz, multitone test technique used. Min. gain < GR < Max. gain f = 50Hz f = 100 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz Sinusoidal Test Method Reference Level = -10 dBm0 DR = -40 dBm0 to -3 dBm0 DR = -50 dBm0 to -40 dBm0 DR = -55 dBm0 to -50 dBm0 Sinusoidal Test Method Reference Level = -10 dBm0 DR = -40 dBm0 to -3 dBm0 DR = -50 dBm0 to -40 dBm0 DR = -55 dBm0 to -50 dBm0 Min. -0.1 Typ. Max. 0.1 Unit dB
GRAF
Receive Gain Variation with frequency (VLr and VFr) HPB = 0
-1.5 -0.5 -1.5
-20 -12 -2 0.5 0.5 0.0 -14
dB dB dB dB dB dB dB
Receive Gain Variation with frequency (VLr and VFr) HPB = 1
-1.5 -0.5 -1.5
0.5 0.5 0.0 -14
dB dB dB dB
GRAL E
Receive Gain Variation with signal level (VFr)
-0.5 -0.5 -1.2
0.5 0.5 1.2
dB dB dB
GRAL L
Receive Gain Variation with signal level (VLr)
-0.5 -0.5 -1.2
0.5 0.5 1.2
dB dB dB
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ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol DXA DXR Parameter Tx Delay, Absolute Tx Delay, Relative Test Condition f = 1600 Hz f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz f = 1600 Hz f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz Min. Typ. 320 290 180 50 20 55 80 180 280 200 110 50 20 65 100 220 Max. Unit s s s s s s s s s s s s s s s s
DRA DRR
Rx Delay, Absolute Rx Delay, Relative
NOISE
Symbol NXP NRP NRS Parameter Tx Noise, P weighted (up to 35dB) Rx Noise, linear weighted (*) (max. gain) Noise, Single Frequency Test Condition VMIC = 0V, DE = 0 Receive PCM code = Positive Zero SI = 0 and RTE = 0 MIC = 0V, Loop-around measurament from f = 0 Hz to 100 kHz MIC = 0V, VCC = 3.0 VDC + 50 mVrms; f = 100Hz to 50KHz PCM Code equals Positive Zero, VCC = 3.0VDC + 50 mVrms, f = 100 Hz - 4 kHz f = 4 kHz - 50 kHz DR input set to -6 dBm0 PCM code 300 - 3400 Hz Input PCM Code applied at DR 4600 Hz - 5600 Hz 5600 Hz - 7600 Hz 7600 Hz - 8400 Hz 30 Min. Typ. -75 120 -50 Max. -70 150 Unit dBm0p Vrms dBm0
PPSRx
PSRR, Tx
dB
PPSRp
PSRR, Rx
30 30
dB dB
SOS
Spurious Out-Band signal at the output
-40 -50 -50
dB dB dB
(*) 300 to 3400Hz bandwidth
CROSSTALK
Symbol CTx-r Parameter Transmit to Receive Test Condition Transmit Level = 0 dBm0, f = 300 - 3400 Hz DR = Quiet PCM Code Receive Level = -6 dBm0, f = 300 - 3400 Hz MIC = 0V Min. Typ. -100 Max. -65 Unit dB
CTr-x
Receive to Transmit
-80
-65
dB
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STW5093
DISTORTION
Symbol STDX(*) Parameter Signal to Total Distortion (up to 35dB gain) Test Condition Sinusoidal Test Method (measured using linear 300 to 3400 weighting) Level = 0 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 0 dBm0 input signal Sinusoidal Test Method (measured using linear 300 to 3400 weighting) Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 -6 dBm0 input signal Sinusoidal Test Method (measured using linear 300 to 3400 weighting) Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 -6 dBm0 input signal Loop-around measurement Voltage at MIC = -10 dBm0 to -27 dBm0, 2 Frequencies in the range 300 - 3400 Hz Min. # Typ. Max. Unit
Typical values are measured with 30.5dB gain
56 56 50 50 48 48 43 43 38 37.5 29 28.5 24 23 15 13
65 64 61 52 42 31 26 16 -80 -56
dB dB dB dB dB dB dB dB dB
SDFx
Single Frequency Distortion transmit
STDRE(*) Signal to Total Distortion (VFr) ( up to 20dB attenuation)
Typical values are measured with 20dB attenuation.
50 48 43 38 29 24 15
64 62 53 43 33 28 18 -80 -50
dB dB dB dB dB dB dB dB
SDFr
Single Frequency Distortion receive (VFr)
STDRL(*) Signal to Total Distortion (VLr) (up to 20dB attenuation) Typical values are measured with 20dB attenuation
50 48 43 38 29 24 15
64 62 53 43 33 28 18 -80 -75 -50 -46
dB dB dB dB dB dB dB dB dB
SDLr MD
Single Frequency Distortion receive (VLr) Intermodulation
(*) The limit curve shall be determined by straight lines joining successive coordinates given in the table. (#) Lower limits used during the automatic testing to avoid unrealistic yield loss due to ae2dB imprecision of time-limited noise measurements.
POWER DISSIPATION
Symbol ICC0 Parameter Power down Current Test Condition CCLK,CI = 0.1V; CS- = VCCIO-0.1V REMOCON function disabled (REN = 0) CCLK,CI = 0.1V; CS- = VCCIO-0.1V REMOCON function enabled (REN = 1) REMIN = VILREM or REMIN = VIHREM VLr+, VLr- and VFr not loaded Min. Typ. 0.4 Max. 5 Unit A
ICC0R
Power down Current
2
10
A
ICC1
Power Up Current
5
8
mA
30/34
STW5093
AUDIO CODEC APPLICATIONS Figure 7. Application Note for Microphone Connections.
SINGLE ENDED MODE MBIAS 1K
1K
DIFFERENTIAL MODE MBIAS
STW5093
2K 4K MICP 22F 0.47F
22F
STW5093
2K 4K MICP 0.47F
MICN
MICN 0.47F 4K
D98TL395
1K
0.47F
4K
D98TL396
Figure 8. Application Note for VLr Connections.
CERAMIC RECEIVERS (50nF) R VLr+ EP VLr+ EP R
D98TL397A
R must be greater then 50 For highes capacitor transducers, lower R values can be used
DYNAMIC RECEIVERS (8)
STW5093
VLr-
STW5093
VLrD98TL398
Figure 9. Application Note for VFr Connections.
CERAMIC RECEIVERS (50nF) R VFr EP
DYNAMIC RECEIVERS (30) C=100F VFr EP
STW5093
STW5093
D98TL409A
R must be greater then 50 For highes capacitor transducers, lower R values can be used
D98TL410
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STW5093
POWER SUPPLY NOTES Two different strategies can be used to minimize power supply noise/interference. a) Recommended strategy: keep analog and digital power supply rails separate. This requires to use two sets of capacitors, one from AVCC to AGND and the other from DVCC to DGND. Figure 10.
AVCC VCCP 10F 100nF AGND AGND VCCA VCC
DVCC
100nF
STW5093
DGND GNDP GNDA GND DGND
D98TL412
AGND
b) Low cost strategy: tie analog and digital power supplies together as close as possible to GND and VCC pins. This allows to use only one set of capacitors between VCC and GND. Figure 11.
VCCP VCCA
VCC 100nF 10F
STW5093
GNDP GNDA GND
D98TL413
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STW5093
mm DIM. MIN. A A1 A2 b c D E e E1 L K 4.30 0.50 0.05 0.85 0.17 0.09 7.70 7.80 6.40 0.50 4.40 0.60 4.50 0.70 0.169 0.020 0.90 TYP. MAX. 1.10 0.15 0.95 0.27 0.20 7.90 0.002 0.033 0.007 0.004 0.303 MIN.
inch TYP. MAX. 0.043 0.006 0.035 0.037 0.011 0.008 0.307 0.252 0.0197 0.173 0.024 0.177 0.028 0.311
OUTLINE AND MECHANICAL DATA
TSSOP30 (Thin Shrink)
0 (min.) 8 (max.)
E1
A2 b
0.010 mm 0.004 inch SEATING PLANE
A
c
e
A1
D Gage Plane 0.25mm 30 16 E Pin 1 identification 15 A1 SEATING PLANE
TSSO30M
k L
33/34
STW5093
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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